1. Field of the Invention
The present invention relates to the field of display technology, and in particular to a method for manufacturing a thin-film transistor (TFT) substrate and a structure thereof.
2. The Related Arts
OLED (Organic Light Emitting Diode) has various advantages, such as being self-luminous, high brightness, wide view angle, flexibility, and low power consumption, and is thus attracting wide attention and, as a new generation of display measure, is gradually taking the place of the traditional liquid crystal display to be used in mobile phone screens, computer monitors, and full-color televisions. Based on the way of driving, OLEDs can be classified as passive matrix OLEDs (PMOLEDs) and active matrix OLEDs (AMOLEDs). The AMOLEDs are often involved with an oxide semiconductor backboard, of which the structure is simpler than a low-temperature poly-silicon (LTPS) backboard.
Referring to FIG. 1, a cross-sectional view is given to illustrate a conventional thin-film transistor (TFT) substrate structure used for active matrix organic light emitting diode (AMOLED), which comprises a base plate 100, a first gate electrode 210 and a second gate electrode 220 formed on the base plate 100, a gate insulation layer 300 formed on the first gate electrode 210, the second gate electrode 220, and the base plate 100, a first semiconductor layer 410 formed on the gate insulation layer 300 and located above the first gate electrode 210, a second semiconductor layer 420 formed on the gate insulation layer 300 and located above the second gate electrode 220, an etch stop layer 500 formed on the first semiconductor layer 410, the second semiconductor layer 420, and the gate insulation layer 300, a first source electrode 610 and a first drain electrode 620 formed on the etch stop layer 500 and located above the first gate electrode 210, a second source electrode 630 and a second drain electrode 640 formed on the etch stop layer 500 and located above the second gate electrode 220, a passivation layer 710 formed on the first source electrode 610, the first drain electrode 620, the second source electrode 630, the second drain electrode 640, and the etch stop layer 500, a planarization layer 720 formed on the passivation layer 710, a pixel electrode layer 800 formed on the planarization layer 720, a pixel definition layer 900 formed on the pixel electrode layer 800 and the planarization layer 720, and photo spacers 920 formed on the pixel definition layer 900.
The etch stop layer 500 comprises two first vias 510 formed therein to correspond to the first semiconductor layer 410 and the etch stop layer 500 comprises two second vias 510 formed therein to correspond to the second semiconductor layer 420. The etch stop layer 500 and the gate insulation layer 300 comprise a third via 530 formed therein to correspond to a side portion of the second gate electrode 220 that is adjacent to the first gate electrode 210. The passivation layer 710 and the planarization layer 720 comprise a fourth via 810 formed therein to correspond to the second source electrode 630. The pixel definition layer 900 comprises a fifth via 910 formed therein to correspond to the pixel electrode layer 800.
The first source electrode 610 and the first drain electrode 620 are connected through the first vias 510 with the first semiconductor layer 410. The second source electrode 630 and the second drain electrode 640 are connected through the second vias 520 with the second semiconductor layer 420. The first source electrode 610 is connected through the third via 530 with the second gate electrode 220. The pixel electrode layer 800 is connected through the fourth via 810 with the second source electrode 630. The fifth via 910 exposes a portion of the pixel electrode layer 800.
Each layer of the first gate electrode 210 and the second gate electrode 220, the gate insulation layer 300, the first semiconductor layer 410 and the second semiconductor layer 420, the etch stop layer 500, the first source electrode 610, the first drain electrode 620, the second source electrode 630, and the second drain electrode 640, the passivation layer 710, the planarization layer 720, the pixel electrode layer 800, the pixel definition layer 900, the photo spacers 920 is manufactured with one photolithographic process. In other words, the TFT substrate shown in FIG. 1 needs ten photolithographic processes in total. The manufacturing process is complicated and the manufacturing efficiency and yield rate may be affected.